1. Field of the Invention
The present invention relates to method for manufacturing semiconductor device, and in particular to a method for manufacturing semiconductor device wherein a channel implant process of a transistor in a DRAM is performed in a self-aligned manner without using any mask to prevent misalignment and to improve a refresh characteristic of the DRAM.
2. Description of the Background Art
In accordance with a conventional method for manufacturing DRAM, only bit line contact region and a channel region of a cell transistor are subjected to a channel implant process using a channel implant mask in order to improve punch-through and data retention characteristics of the cell transistor.
FIGS. 1a through 1e are cross-sectional diagrams illustrating a conventional method for manufacturing semiconductor device comprising a channel implant process.
Referring to FIG. 1a, a pad oxide film 13 and a pad nitride film 15 are sequentially formed on a semiconductor substrate 11 such as a silicon wafer.
The pad nitride film 15, the pad oxide film 11 and a predetermined thickness of the semiconductor substrate 11 are etched via a photoetching process using a device isolation film mask (not shown) to form a trench 17.
Now referring to FIG. 1b, a device isolation film 19 filling the trench 17 is formed. Preferably, the device isolation film 19 is formed by depositing an oxide film for device isolation film filling the trench 17 on the entire surface, and then planarizing and wet-etching the oxide film.
Referring to FIG. 1c, the pad nitride film 15 is removed preferably using phosphoric acid. A predetermined thickness of the device isolation film 19 is etched during the removal process of the pad nitride film 15.
Thereafter, a deep n-well 21 is formed via an implant process using an n-well mask (not shown). A p-well 23 is formed in the deep n-well 21 via an implant process using a p-well mask (not shown).
Referring to FIG. 1d, the pad oxide film 13 is removed to expose the semiconductor substrate 11. A buffer oxide film 25 is then formed on the exposed portion of the semiconductor substrate 11. Thereafter, a photoresist film pattern 29 is formed on the semiconductor substrate 11. The photoresist film pattern 29 is formed via an exposure and development process using a channel implant mask (not shown) to expose a bit line contact region A and a channel region B. The channel region B resides on both sides of the bit line contact region A. Each region has a width of 1F which is the minimum line width. A storage electrode contact region C resides adjacent to the channel region B. That is, the region A having a width of 1F resides in the center of the active region between the device isolation film 19 and the regions C having a width of 1F resides at both sides of region A and the region B having a width of 1F resides therebetween.
When the channel implant process is performed using the misaligned photoresist film pattern 29, which is shown as a dotted line in FIG. 1d, the impurity concentrations of the regions A, B and C differ from desired concentrations. The differences degrade the characteristic of the device.
For example, the concentration of impurity implanted in the partially exposed channel region is smaller than the desired concentration. This reduces the threshold voltage Vt to induce a short channel effect. Moreover, when an impurity is implanted in the storage electrode contact region due to misalignment of the photoresist film pattern, the concentration of the storage electrode contact region where the impurity is implanted is higher than that of the storage electrode contact region where the impurity is not implanted. This increases the electric field, resulting in an increase in junction leakage current and degradation of data retention.
Now referring to FIG. 1e, the photoresist film pattern 29 and the buffer oxide film 25 are sequentially removed. A gate oxide film 31 is then formed on a surface of the semiconductor substrate 11. Next, a stacked structure of a polysilicon film 33 for gate electrode, a tungsten nitride barrier film 35, a tungsten film 37 for gate electrode and a hard mask film 39 is formed on the gate oxide film 31.
Thereafter, the stacked structure is patterned via a photoetching process using a gate electrode mask (not shown) to form a gate electrode (not shown).
In accordance with the conventional method for manufacturing semiconductor device, the misalignment of the photoresist film pattern used as a channel implant mask during the channel implant process causes variation of the concentration of the active region, resulting in generation of short channel effect and degradation of delay retention characteristics.